METHODOLOGY

Bespoke Model Delivery

A trained model binary and an 8-section silicon-verified scorecard, delivered for your detection problem on your chip. From Feasibility Gate through on-silicon validation.

8-SECTION SCORECARD

01AccuracyCross-validation accuracy on auto-labeled dataset. On-silicon inference results.
02LatencyInference latency measured on physical hardware. Per-class and average figures.
03EnergyOn-silicon power draw from supply rail. Pending rig commissioning for current engagements.
04Memory footprintFlash and RAM consumption of the deployed model binary.
05Data provenanceAuto-labeled dataset origin, capture conditions, class balance, and coverage.
06Model topologyArchitecture, quantization scheme, layer counts, and INT8 conversion notes.
07Deployment environmentTarget chip, toolchain, firmware integration instructions.
08Re-verification scheduleRecommended cadence for re-runs on updated data or new silicon revisions.

The scorecard is structured as a compliance artifact aligned to MLPerf Tiny and EnergyRunner methodology. Regulated customers have used it directly in EU AI Act technical files.

WHAT MAKES THIS DIFFERENT

Auto-labeled data

The rig captures sensor-chain data and labels it automatically during the Feasibility Gate. No hand-labeling. The dataset becomes your asset.

Real sensor-chain training

The model trains on data captured from the actual sensor chain of your product. No augmentation shortcuts. The gap between training conditions and deployment conditions is as small as the rig can make it.

On-silicon energy measurement

Power is read from the supply rail of your chip under inference load. Not estimated. Not modeled. Read from the pin. Energy measurement is pending rig commissioning for current engagements.

Chip-agnostic delivery

The trained binary and scorecard are delivered for your silicon. Any MCU or NPU with a standard flash interface qualifies. The rig adapts to the chip, not the other way around.

PROCESS

01

Feasibility Gate

Go/no-go report with preliminary accuracy and latency on your actual chip. Required before Bespoke Model Delivery. The dataset captured here carries forward.

02

Dataset build

Auto-labeled sensor-chain data is expanded to full training volume. Chrysalis manages capture, labeling, and quality gates.

03

Model training

Training runs against the expanded dataset under the conditions of your deployment environment. INT8 quantization for MCU targets.

04

On-silicon validation

The trained model goes back on the rig. Accuracy, latency, and energy are measured on your physical hardware.

05

Scorecard and binary delivery

You receive the trained model binary plus the 8-section silicon-verified scorecard. The scorecard is structured as a compliance artifact.

Bespoke Model Delivery requires a completed Feasibility Gate first. The go/no-go report and the auto-labeled dataset from the gate carry forward into this engagement.

EU AI ACT

Conformity artifact angle

Article 9 of the EU AI Act requires ongoing risk-management documentation for high-risk AI systems, including audit trails for model changes. The 8-section scorecard is structured to serve as a conformity artifact directly. Section 8 specifies a re-verification schedule, which the Monitoring and Re-verification Subscription automates.

WHAT THE SCORECARD COVERS FOR COMPLIANCE

  • Data provenance and capture conditions
  • On-silicon accuracy and latency evidence
  • Model topology and quantization record
  • Deployment environment specification
  • Re-verification schedule for ongoing compliance

START AN ENGAGEMENT

Send the chip, the problem, and the modality.

We return a go/no-go within the feasibility window.

Emailchrysalis@sogoodmail.co
Feasibility gate€3,500 fixed price
TurnaroundWithin feasibility window

Submitting this form starts no billing. The Feasibility Gate engagement is priced at €3,500 and confirmed separately.

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