METHODOLOGY
Feasibility Gate
A go/no-go report with preliminary accuracy and latency measured on your actual chip. Before you commit to a fixed-price engagement, know whether the detection problem is solvable on your silicon.
WHAT THE GATE DELIVERS
Silicon measurement, not simulation
Every accuracy and latency figure in the Feasibility Gate report comes from the hardware-in-the-loop rig. Your chip goes into the loop. The rig stimulates the sensor chain, captures the response, runs inference on the device, and reads the result from physical hardware.
The methodology aligns to MLPerf Tiny and EnergyRunner. Energy measurement is pending rig commissioning and is not included in the current gate output.
RIG METHODOLOGY OVERVIEW
- Hardware-in-the-loop: physical chip, not a simulator
- Sensor-chain stimulation with real or representative stimuli
- Auto-labeled dataset capture for reuse downstream
- Accuracy and latency measured on-device
- MLPerf Tiny and EnergyRunner methodology alignment
PROCESS
01
Ship the chip
You send your silicon. Any MCU or NPU with a standard flash interface qualifies. Unusual packages require a short pre-qualification call first.
02
Rig flash
The hardware-in-the-loop rig instruments your chip. No emulation. The physical device goes into the measurement loop.
03
Stimulate and capture
The rig drives the sensor chain with real stimuli and captures the response from the physical device.
04
Auto-label
Chrysalis auto-labels the captured sensor data. This is the same pipeline used for Bespoke Model Delivery, so the output is reusable.
05
Measure
Inference runs on your chip. Accuracy and latency are measured from physical hardware, not a simulator. Energy measurement is pending rig commissioning.
06
Scorecard delivered
You receive a go/no-go report with preliminary accuracy and latency figures, a dataset summary, and a recommended next step.
WHAT YOU PROVIDE
- Your chip (MCU or NPU, standard flash interface)
- Detection problem statement and target modality
- Sample data or a description of the acoustic environment
- A point of contact for pre-qualification questions
WHAT YOU RECEIVE
- Go/no-go feasibility report
- Preliminary accuracy figure from hardware-in-the-loop measurement
- Preliminary latency figure from your actual silicon
- Auto-labeled dataset summary (reusable for Bespoke Model Delivery)
- MLPerf Tiny and EnergyRunner aligned methodology notes
- Recommended next step with rationale
START AN ENGAGEMENT
Send the chip, the problem, and the modality.
We return a go/no-go within the feasibility window.